The present invention relates to a field of manufacturing liquid crystal display, and particularly to a liquid crystal cell test.
At present, liquid crystal cell tests for TFT-LCD (Thin Film Transistor-Liquid Crystal Display) are mostly focused on realizing different test pictures by changing data signals, the purpose of which is to make various badness of liquid crystal display panels all in a special test picture, so that positions in which the badness are located are tested and determined by eyeballing of an operator. However, this test means in which different test pictures are realized by only changing data signals does not think much of the important sense of the gate scan signal in testing, and thus many defects of the liquid crystal display panel, such as short circuit badness of data line and gate scan line or the like, can not be fully displayed on the test pictures. Therefore, this test means can not completely reflect badness phenomena, and it is difficult for the operator to obtain exact coordinate information of the badness positions, which renders great difficulty in maintaining, analyzing and improving.
The gate scan signal is carried by the gate scan line. In a same picture, a TFT turned-on voltage is output by the gate scan line of a certain row only once for about 10-30 μs, the voltage value thereof is usually 15 to 30 Volts, and the gate scan line is in a state of outputting the gate scan signal being turned off for the rest time, the voltage value thereof is usually −3 to −10 Volts. A signal voltage carried by the data line is picture information to be displayed, which generally is about 0-15 volts. For example, in a normally white mode of the picture, a signal voltage with a maximum absolute value with respect to a voltage of a common electrode represents black picture information.
The short circuit badness of the data line and gate scan line is an interference problem caused by electrical short circuit, and is referred to as a DGS (Data Gate Short Circuit) badness. The data line in which a DGS badness locates is controlled by gate scan line OFF signal (negative voltage signal) for most time, and thus a voltage grads is formed along the data line direction, which is minimum at a crossing point of the short circuit.
As shown in FIG. 1, at present, a test apparatus for a liquid crystal cell comprises a test signal generator 200, a direct current module 300, a timing controller 400 connected with the test signal generator 200, a gate driver 500 connected with the direct current module 300 and the timing controller 400, and a source driver 600 connected with the timing controller 400. In the test, the test signal generator 200 generates a test signal and outputs it to the timing controller 400; the direct current module 300 generates a high level signal and a low level signal; the gate driver 500 modulates the high and low level signals with a frame-on control signal generated by the timing controller 400 so as to output a gate scan signal; the timing controller 400 outputs a gray scale picture signal at the same time, and drives pixel units through the source driver 660. Therefore, a picture of test result can be displayed on the screen.
As shown in FIG. 2, in a post-assembly test, for a conventional L0 test picture for example, a line with gradually changed brightness appears on the short-circuit data line due to the voltage grads formed along the direction of the data line in which the DGS badness locate, but the position of the badness is not clear. When outputting a turning-on signal, the voltage of the gate scan line in which the DGS badness locate drops due to the influence of the gray scale picture signal on the data line, which renders the charging current of all the TFTs in that gate scan line declines, i.e. insufficient charging; whereas when outputting a turning-off signal, the voltage of the gate scan line rises up due to the influence of the gray scale picture signal on the data line, which renders an increase of the turning-off current of all the TFTs in that gate scan line, that is, the turning-off current can not be maintained. However, although the respective pixel electrode voltages are influenced by the short circuit of the gate scan line and data line, in a normal progressive scan process, the influence can not be clearly displayed and recognized by the operator as compared with neighbor lines. Accordingly, the crossing point of the questionable gate scan line and data line can not be determined, that is, the position of the DGS badness is not clear.